fpga
ورود به سایت این آگهی USB2.0 + the Cyclone FPGA development board

the characteristics
Comply with USB 2.0 specification, 480Mbps high-speed transport protocol standard, compatible with USB1.1
Enhanced type of Cypress EZ-USB FX2LP family of processors CY7C68013A-128AXC encompasses enhanced USB the Core, high-speed 8051 Core and 16K of RAM, the GPIF interface, the Slave FIFO interface, all transfer types (bulk, interrupt, control of transmission)
Complete on-line simulation and debugging programs, the Keil full-window development environment, no emulator will be able to simulation debugging
Complete in-system programming solutions, 8K bytes of program memory space (EEPROM), no programmer can directly through the control panel on the development system repeatedly programmed code
Complete system to download the program to the development of the system is running, through the control panel to download 64K bytes of program
FPGA resources, the Cyclone EP1C6Q240C8 FPGA
Serial FPGA configuration chip EPCS4, the capacity of more than four times the EPCS1 fully meet the complex design requirements
Expansion of two 256K × 16bit SRAM FPGA outside the model IS61LV25616-10T, data, address, line of control is completely independent, suitable for use as the ping-pong cache to achieve high-capacity data acquisition
The complete Chinese development document
Experimental examples, including the bulk transfer, interrupt transmission, transmission control, the FX2 transfer speed test, the IO port control, the GPIF test, test SLAVE FIFO, USB to serial test, the serial port to USB test BulK transmission test
Has been established (VC6.0) firmware (the Keil C51), driver (DDK and DriverStudio) and application development environment (engineering)
GPIF and the SLAVE FIFO transmission support 8/16 bit bus mode, the endpoint FIFO and peripheral seamless connection

the hardware resources and functions

CY7C68013A-128AXC chip (128pin): with an enhanced 8051 core, clocked at 48Mhz, with 16K of internal RAM
Cyclone EP1C6Q240C8 the FPGA, with 5,980 logic cells, and 92,160 one-bit embedded RAM, two phase-locked loops (PLLs), 185 user I / O pins, you can use Altera\\\'s Nios soft core and a rich IP library, and quickly realize complete programmable chip (SOPC)
Serial FPGA configuration chip EPCS4, the capacity of more than four times the EPCS1 fully meet the complex design requirements
Expansion of two 256K × 16bit SRAM FPGA outside the model IS61LV25616-10T, data, address, line of control is completely independent, suitable for use as the ping-pong cache to achieve high-capacity data acquisition
24M active oscillator, JTAG and AS configuration interface
RS232 serial port: two, one is available to users or another for the Keil debugger (the MAX3232)
EEPROM: used to store the VID / PID or firmware, EEPROM capacity can be selected by jumper, the default configuration 24LC64 (8K)
64K of program data space (IS63LV1024), USB
3 key 4 LED LED
Keil software simulation debugging capabilities (64K program and data space)
Online to download and in-system programmable feature
Bus or an external power supply optional
GPIF and SLAVE pin is connected to the FPGA and the the 40PIN outer expansion socket
4-layer design, stable and reliable

the software CD
Of CYPRESS the EZ-USB on the FX2 Development Kit
EZ-USB Control Panel (Control Panel) software and source code (VC project)
The EZ-USB generic driver and source code (VC project, the DDK development)
EZ-USB generic driver instead of driver source code (VC project, DriverWorks development)
EZ-USB FX2 firmware load device drivers and sample source code (VC Engineering)
EZ-USB FX2 application framework and source code (VC project)
EZ-USB FX2 firmware library and source code
FPGA source code (the Quartus II project file, Verilog HDL)
Application source code (VC Engineering)
Presented a large cache drive (2M bytes of cache, the default drive is 64K bytes)
Complete circuit diagram, exactly the same assurance and development board
The tools needed software development process; Bushound, the DDK, the DS, Keil, the Quartus II
Detailed and complete development documentation
USB1.1 2.0 protocol information in English, Cyclone FPGAs drive the development of books and other large amounts of data

متعلقات:
Board -
USB2.0 shielded wire -
Standard serial line -
پروگرامر usb چیپ های altera usb blaster-
CD-

قیمت 480000 تومان

تصویر محصول:

به روز آوری: سه شنبه, 24 دی 1392
قیمت: 4800000

تلفن :	منقضی شده
منطقه :	استان تهران
آدرس :	استان تهران - تهران

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در مورد: USB2.0 + the Cyclone FPGA development board

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